VSD - Signal Integrity

Course details

Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three. 

Crosstalk is the interference caused due to communication between the circuits

Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.

Course Details:
•Reasons for Crosstalk

•Introduction to Noise Margin

•Crosstalk Glitch Example

•Factors Affecting Glitch Height

•AC Noise Margin

•Timing Window Concepts

•Impact of Crosstalk on Setup and Hold Timing

•Techniques to reduce Crosstalk

•Power Supply Noise