SystemVerilog Assertions & Functional Coverage FROM SCRATCH

Course details

SystemVerilog Assertions and Functional Coverage is a comprehensivefrom-scratch course on Assertions and Functional Coverage that covers featuresof SV LRM 2005/2009 and 2012. The course does not require any priorknowledge of OOP or UVM. The course is taught by a 30 year veteran in thedesign of CPU and SoC who published a book on SVA and FC in 2014 and hold 13U.S. patents on design verification. The course has 33 lectures and is 8.5hours in length that will take you step by step through learning of thelanguages.

The knowledge gained from this course will help you find and coverthose critical and hard to find and cover design bugs. SystemVerilogAssertions and Functional Coverage are very important parts of overallfunctional verification methodology and all verification engineers needthis knowledge to be successful. The knowledge of SVA and FCwill indeed be highlights of your resume when seeking a challengingjob or project The course offers step-by-step guide to learning of SVA and FC withplenty of real life applications to help you apply SVA and FCto your project in shortest possible time. SVA and FC helps criticalaspect of Functional/Temporal domain coverage which is simply notpossible with code coverage.