Course details
A course that will teach you everything about System Verilog Assertions (SVA) and Functional coverage coding which forms the basis for the Assertion based and Coverage Driven Verification methodologies. These are the two most widely used methodologies in current SOC/chip designs, The course covers everything from concepts to coding along with several examples to illustrate as well as quizzes and lab exercises to make your learning thorough.
The course contents include several examples and illustrations from LRM and other popular books on SystemVerilog
Updated on 08 November, 2015
