تفاصيل الدورة

This course was designed to give students an opportunity to kick-start their skills to Design Digital Electronics WITHOUT the hurdle of having to code in HDL.

How this course works

Concepts are first explained, then demonstrated by using the ISE software from Xilinx. Coding in HDL languages will not be taught in this course but instead, Schematics will be used as it is easier for beginners. Students will only need drag, drop and connect schematic symbols together. Then Run through the flow of ISE to generate the bit file.The bit file will be downloaded on the board to see the results.

The goal is to quickly put together designs and try them on the board, without the hurdle of VHDL/Verilog coding. In this way, you will focus on how Digital Electronics works.

This course doesn't show software simulation but focuses on testing your designs straight on the board.

What will you need?

You will need to download and install Xilinx ISE software in the Webpack version, which is free. Ideally you will need the Basys 2 board, which uses the Spartan 3E FPGA, to verify your design on hardware.

 Content

The course is split in sections of the main building blocks of Digital Electronics such as Registers, Logic Gates, Random Access memory etc...

In each section there is explanation of various blocks e.g in the Registers section will be explained the Flip Flops and Shift Registers. After most blocks explanation there will be a practical activity on how to implement the circuit on an FPGA and verify the design on the Basys 2 board. 

Quizzes

There is a generous number of quizzes between the lessons to help the students keep focused and find the course fun to undertake. 

Practical 

Most of the Practical Activities will be simply to load the design on your Basys2 board and use the switches as input & LEDs as output. Additionally, at the end of the course, you will also learn how to connect the board to other external components using JTAGs through the use of wires and a breadboard. 

تحديث بتاريخ 19 February, 2018
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