FPGA Design with High Level Synthesis Tool (VIVADO HLS) هذه الدورة تدرس باللغة الإنجليزية

تفاصيل الدورة

High Level Synthesis is new approach on FPGA Design with C/C++ Language.This Course covers "How to Install VIVADO along with HLS,  Creating new project on HLS, Running C Simulation on HLS, Synthesizing the HLS Project's which converts C/C++ Source in to Verilog/VHDL and System C, Running C/RTL Co-simulation, Implementing HLS Design in to IP core Format or Exporting HLS Design to VIVADO IPI.

After Completing this course you will be able to Design, Simulate,Synthesize and Implement/Export HLS projects. HLS includes large number of C/C++ Libraries for Computer Vision (OpenCV), Video/Image Processing and Mathematical Computations which is very much complex while implementing on HDL/RTL. So HLS is flexible and easy way for implementing such AI and Math Algorithm on FPGA.

In this Lab you are going to do lab on Design, Simulation , Synthesis and Implementation (Export Design) of Counter, Matrix Multiplier, Frequency Modulator, Numerically Controlled Oscillator (NCO Design) in C++. You will also integrate the exported HLS project with Zynq Processing System at VIVADO IP Integrator and Synthesize, Implement the Project on VIVADO IPI.